1. Field of the Invention
This invention relates to a semiconductor device, and more particularly to a semiconductor device having voltage stress testing pads for effecting a screening test to eliminate defective elements by use of a probe card and a prober in a state (wafer state) in which the semiconductor wafer is not yet divided into chips.
2. Description of the Related Art
In general, in a semiconductor device manufacturing process, non-defective elements are selected by the die sort test after completion of the wafer manufacturing process, defective elements are marked and then the non-defective elements are set into packages to make finished products. The semiconductor device in the form of a finished product (after the packaging operation) is subjected to a burn-in process.
A semiconductor memory (which is suitable for a method of effecting the screening test to eliminate defective elements by use of a probe card and a prober in the wafer state before the die sorting operation is used) is proposed in U.S. patent application Ser. No. 07/544,614, now abandoned.
According to the above semiconductor memory, when the screening test is effected by use of the probe card and prober in the wafer state, the screening test for the individual memory chip areas can be efficiently effected in a short period of time.
When the probes of the probe card are simultaneously set in contact with voltage stress testing pads on a plurality of chip areas of the wafer to apply the voltage stress in the screening operation in the wafer state, the following problems may occur if the number of voltage stress testing pads for each chip is large.
(a) When there does not exist a sufficiently large space for arranging pads on the chip, the chip size must be increased if the voltage stress testing pads are to be added.
(b) When the number of probes of the probe card is increased according to the number of pads, it becomes difficult to attain the good flat contact between the front end of the probe and the pad. When the front end of the probe of the probe card cannot be made sufficiently flat, the pad and the probe of the probe card may be damaged and the durability of the probe will be degraded.
(c) When the number of probes of the probe card is increased according to the number of pads, it becomes necessary to significantly enhance the voltage supplying ability of a tester connected to the probe card, thereby raising the cost of the tester.
(d) When the distance between the pads is smaller than the minimum pitch of the probes of the probe card, the number of chips which can be simultaneously set in contact with the probes of the probe card is limited.
(e) The limitation on the arrangement of pads becomes severe and it becomes difficult to arrange the pads in such a pattern that a large number of chips can be simultaneously subjected to the screening test in the wafer state.
Therefore, in a semiconductor device having voltage stress testing pads for effecting the screening test to eliminate defective elements in the wafer state, it is desirable to reduce the number of voltage stress testing pads for each chip.